intersil Manuals

The ISL6118 is Intersil's dual channel, fully independent overcurrent (OC) fault protection IC for the +2.5V to +5.5V environment. This device features internal current monitoring, accurate current limiting, integrated power switches and current limited delay to latch-off for system protection. The ISL6118 current sense and limiting circuitry sets the current limit to a nominal 0.6A, which is well suited for the 3.3V AUX ACPI application. The ISL6118 is the ideal companion chip to the HIP1011D and HIP1011E dual PCI hot plug controllers. Together these and the ISL6118 fully control the four legacy PCI voltages (±12V, +3.3V, +5V) and the 3.3V AUX, respectively, for power control of two PCI slots compliant to PCI Bus Power Management Interface Spec Rev 1.1. Designed to be co-located with the HIP1011D on the motherboard, the ISL6118 provides OC fault notification, accurate current limiting and a consistent timed latch-off thus isolating and protecting the voltage bus in the presence of an OC event or short circuit during all PCI Bus Power States as defined by the PCI specification. The 12ms time to latch-off ensures that the system does not experience an overcurrent event during PCI bus power state transitions.

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ISL6119 is a USB dual port power controller from Intersil that provides fully independent overcurrent (OC) fault protection. This device operates over the +2.5V to +5.5V range and features internal current monitoring, accurate current limiting, integrated power switches and current limited delay to latch-off for system protection. The ISL6119 current sense and limiting circuitry sets the current limit to a nominal 1A, making this device well suited for the USB port power management application. The ISL6119 provides OC fault notification, accurate current limiting and a consistent timed latch-off thus isolating and protecting the voltage bus in the presence of an OC event or short circuit. The 12ms time to latch-off is independent of the adjoining switch’s electrical or thermal condition and the OC response time is inversely related to the OC magnitude. Each ISL6119 incorporates in a single 8 lead SOIC package two 80mΩ N-channel MOSFET power switches for power control. Each switch is driven by a constant current source giving a controlled ramp up of the output voltage. This provides a soft start function to prevent current overshoot.

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The ICL7673 is a low-cost automatic battery backup switch that can automatically connect the output to the higher voltage of the two power supplies

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The HMP8170 NTSC and PAL encoder is a high-quality video encoder that supports YCbCr digital video data driving P0-P15 inputs, optionally lowpass filtered to 6MHz and driving the Y analog output. Cb and Cr are each lowpass filtered to 1.3MHz, quadrature modulated, and added together. The result drives the C analog output. The digital Y and C data are also added together and drive the two composite analog outputs. The DACs can drive doubly-terminated (37.5Ω) lines, and run at a 2x oversampling rate to simplify the analog output filter requirements.

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The HMP8154 and HMP8156A are NTSC and PAL encoders that are used to convert digital image data into high-quality NTSC and PAL video

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The HMP8117 is a high quality NTSC and PAL video decoder with internal A/D converters. It is compatible with NTSC M, PAL B, D, G, H, I, M, N, and combination N (NC) video standards. Both composite and S-video (Y/C) input formats are supported. A 2-line comb filter plus a user-selectable chrominance trap filter provide high quality Y/C separation. User adjustments include brightness, contrast, saturation, hue, and sharpness. Vertical blanking interval (VBI) data, such as Closed Captioning, Wide Screen Signalling and Teletext, may be captured and output as BT.656 ancillary data. Closed Captioning and Wide Screen Signalling information may also be read out via the I2C interface. The Videolyzer™ feature provides approved Macrovision™ copy-protection bypass and detection.

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The ISL5314 is a complete Direct Digital Synthesizer (DDS) system, integrating a 48-bit programmable Carrier NCO and a high-speed 14-bit DAC. It supports parallel processor interface and asynchronous serial interface, with modulation control and frequency control capabilities.

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The ISL5217 Quad Programmable UpConverter (QPUC) is a QASK/FM modulator/FDM upconverter designed for high dynamic range applications such as cellular basestations. It combines shaping and interpolation filters, a complex modulator, and timing and carrier NCOs into a single package. Each QPUC can create four FDM channels, and multiple QPUCs can be cascaded digitally to provide for up to 16 FDM channels in multi-channel applications. The ISL5217 supports both vector and FM modulation, with multiple modulation modes and filtering options.

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The Intersil HSP45116A is a high-performance quadrature numerically controlled oscillator/modulator that combines a complex NCO and a high-speed 16-bit complex multiplier/accumulator. It allows for multiplication and modulation of complex vectors. The product features a 32-bit phase resolution and a frequency resolution better than 0.013Hz at 52MHz. The complex sinusoid output has a spurious free dynamic range greater than 90dBc.

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The Intersil HSP45102 is a Numerically Controlled Oscillator (NCO12) with 32-bit frequency resolution and 12-bit output. With over 69dB of spurious free dynamic range and worst case frequency resolution of 0.009Hz, the NCO12 provides significant accuracy for frequency synthesis solutions at a competitive price.

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The HSP9501 is a 10-bit wide programmable data buffer designed by Intersil and is used in high speed digital systems. The buffer can be selected to operate in two different modes: delay mode and data recirculate mode. In the delay mode, a programmable data pipeline is created which can provide 2 to 1281 clock cycles of delay between the input and output data. In the data recirculate mode, the output data path is internally routed back to the input to provide a programmable circular buffer. The length of the buffer or amount of delay is programmed through the use of the 11-bit Length Control Input Port (LC0-10) and the Length Control Enable (LCEN). An 11-bit value is applied to the LC0-10 inputs, LCEN is asserted, and the next selected clock edge loads the new count value into the Length Control Register. The delay path of the HSP9501 consists of two registers with a programmable delay RAM between them, therefore, the value programmed into the Length Control Register is the desired length - 2. The range of values which can be programmed into the Length Control Register are from 0 to 1279.

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The HSP50415 Wideband Programmable Modulator (WPM) is a quadrature amplitude modulator/upconverter designed for wideband digital modulation. The WPM combines shaping and interpolation filters, a complex modulator, timing and carrier NCOs and dual DACs into a single package. The HSP50415 supports vector modulation, accepting up to 16-bit In phase (I) and Quadrature (Q) samples to generate virtually any quadrature AM or PM modulation format. A constellation mapper and 24 Symbol span interpolation shaping filter is provided for the input baseband signals. Gain adjustment is provided after the shaping FIR filter. A timing error generator in the input section allows the on-chip timing NCO to track the input timing. The WPM includes a Numerically Controlled Oscillator (NCO) driven interpolation filter, which allows the input and output sample rate to have a non-integer or variable relationship. This re-sampling feature simplifies use of sample rates that do not have harmonic or integer frequency relationships to the input data rate and decouples the carrier from the DATACLK. A complex quadrature modulator modulates the baseband data on a programmable carrier center frequency. The WPM offers digital output spurious Free Dynamic Range (SFDR) that exceeds 70dB at the maximum output sample rate of 100MSPS, for input sample rates as high as 25MSPS. X/SIN(X) rolloff compensation filtering is provided. Real 14-bit digital output.

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The ISL5239 Pre-Distortion Linearizer (PDL) is a full featured component for Power Amplifier (PA) linearization to improve PA power efficiency and reduce PA cost.

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The ISL5416 is a four-channel wideband programmable digital downconverter designed for high dynamic range applications such as cellular basestations where the processing of multiple channels is required in a small physical space.

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The ISL5216 is a quad programmable digital downconverter designed for high dynamic range applications such as cellular basestations where multiple channel processing is required in a small physical space.

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The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. It performs down conversion, decimation, narrowband low pass filtering, gain scaling, resampling, and Cartesian to Polar coordinate conversion.

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The HSP50016 is a high performance digital down converter that performs down conversion, filtering and decimation on sampled data streams of up to 16 bits in width and up to a 75 MSPS data rate.

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The HSP43220 Decimating Digital Filter is a linear phase low pass decimation filter which is optimized for filtering narrow band signals in a broad spectrum of a signal processing applications. The HSP43220 offers a single chip solution to signal processing applications which have historically required several boards of ICs. This reduction in component count results in faster development times as well as reduction of hardware costs. The HSP43220 is implemented as a two stage filter structure. As seen in the block diagram, the first stage is a high order decimation filter (HDF) which utilizes an efficient sample rate reduction technique to obtain decimation up to 1024 through a coarse low-pass filtering process. The HDF provides up to 96dB aliasing rejection in the signal pass band. The second stage consists of a finite impulse response (FIR) decimation filter structured as a transversal FIR filter with up to 512 symmetric taps which can implement filters with sharp transition regions. The FIR can perform further decimation by up to 16 if required while preserving the 96dB aliasing attenuation obtained by the HDF. The combined total decimation capability is 16,384. The HSP43220 accepts 16-bit parallel data in 2’s complement format at sampling rates up to 33MSPS. It provides a 16-bit microprocessor compatible interface to simplify the task of programming and three-state outputs to allow the connection of several ICs to a common bus. The HSP43220 has low power consumption and operates over a wide supply voltage range of 1.8V to 3.3V and does not require an external clock.

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