National Manuals (Industrial)

DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link— 65 MHz. The product converts 21 bits of CMOS/TTL data into three LVDS data streams and parallel transmits a phase-locked transmit clock and data streams over a fourth LVDS link. At a transmit clock frequency of 65 MHz, 21 bits of input data are sampled and transmitted every cycle of the transmit clock. With a 65 MHz clock, the data throughput is 171 MB/s. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

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Find DS90CF562MTD suppliers

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DS90C402 is a dual low voltage differential signaling (LVDS) receiver from National Semiconductor Corporation. It features ultra low power dissipation and can operate at data rates up to 155.5 Mbps.

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The DS90C401 is a dual driver device optimized for high data rate and low power applications. This device along with the DS90C402 provides a pair chip solution for a dual high speed point-to-point interface. The DS90C401 is a current mode driver allowing power dissipation to remain low even at high frequency. In addition, the short circuit fault current is also minimized. The device is in a 8 lead small outline package. The differential driver outputs provides low EMI with its low output swings typically 340 mV.

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DS90CF383B is a +3.3V programmable LVDS transmitter from ST. It supports 24-bit FPD link and transmit frequency up to 65MHz. This device uses falling edge trigger, and can be used with DS90CF386 (falling edge trigger receiver) to solve the EMI and cable size problems associated with wide, high speed TTL interfaces.

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The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second). The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit FPD-Link receivers. This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications.

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DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA General Description

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DS90C385A +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display Link-87.5 MHz

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The DS90C383B is a +3.3V programmable LVDS transmitter that supports 24-bit flat panel display (FPD) links-65 MHz

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The DS90C383A/DS90CF383A +3.3V Programmable LVDS Transmitter is a device that converts 28 bits of CMOS/TTL data into four LVDS data streams. It features high-speed transmission and low power consumption, making it suitable for flat panel display applications.

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DS90C383/DS90CF384 is a +3.3V programmable LVDS transmitter and receiver for a 24-bit flat panel display (FPD) link. They support a clock frequency of 65 MHz and utilize high-speed data transmission and low voltage differential signaling technology. The transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS data streams while transmitting a phase-locked clock. The receiver converts the LVDS data streams back into 28 bits of LVCMOS/LVTTL data. They are ideal for solving EMI and cable size problems associated with wide, high-speed TTL interfaces.

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DS90C385 / DS90C365 is a 3.3V programmable LVDS transmitter that converts 24-bit or 18-bit LVCMOS / LVTTL data into four LVDS (low voltage differential signaling) data streams.

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The DS90C365A is a programmable LVDS transmitter designed for 18-bit flat panel display links with a transmission rate of 85 MHz. It converts 21 bits of LVCMOS/LVTTL data into four LVDS data streams and transmits a phase-locked transmit clock in parallel with the data streams over the fourth LVDS link. The transmitter can be triggered by either rising or falling edge strobe. This product is ideal for solving EMI and cable size problems associated with wide, high-speed TTL interfaces, and it supports spread spectrum clocking.

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The data sheet introduces the DS90C385/DS90C365 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz, +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-85 MHz data sheet. The data sheet introduces the features and characteristics of the product.

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The DS90C363B is a 3.3V programmable LVDS transmitter that converts 21 bits of CMOS/TTL data into three LVDS data streams. It supports a transmit clock frequency of 65 MHz, with a transmission rate of 455 Mbps per LVDS data channel, resulting in a data throughput of 170 Mbytes/sec. The transmitter can be programmed for rising edge or falling edge strobe mode through a dedicated pin. This product is ideal for solving EMI and cable size issues associated with wide, high-speed TTL interfaces.

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The DS90C363A/DS90CF363A +3.3V Programmable LVDS Transmitter is a transmitter that converts 21 bits of CMOS/TTL data into three LVDS data streams. It can transmit 18 bits of RGB data and 3 bits of LCD timing and control data at a rate of 455 Mbps per LVDS data channel with a clock frequency of 65 MHz.

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The DS90C363/DS90CF364 is a TI company's 3.3V programmable LVDS transmitter and receiver that supports 20 to 65MHz shift clock, supports programmable transmitter (DS90C363) strobe select (rising or falling edge strobe), single 3.3V power supply, and low chip set (Tx + Rx) power consumption.

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The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color receiver is designed to be used in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs

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The DS90C3201 is a 3.3V single/dual FPD-Link 10-bit color transmitter designed for use in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs. The DS90C3201 is designed to interface between the digital video processor and the display device using the low-power, low-EMI LVDS (Low Voltage Differential Signaling) interface. The DS90C3201 converts up to 70 bits of LVCMOS/LVTTL data into ten LVDS data streams. The transmitter can be programmed clocking data with rising edge or falling edge clock. Optional two-wire serial programming allows fine tuning in development and production environments. At a transmitted clock frequency of 135 MHz, 70 bits of LVCMOS/LVTTL data are transmitted at an effective rate of 945 Mbps per LVDS channel. Using a 135 MHz clock, the data throughput is 9.45 Gbit/s (945 Mbytes/s). This allows the dual 10-bit LVDS Transmitter to support HDTV resolutions.

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