MOTOROLA Manuals

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MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. It features a maximum clock-to-output delay, dual differential outputs, master reset, and scan output.

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The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to conserve array output cell functionality and also output pins. The input shift register is designed with control logic which greatly facilitates its use in boundary scan applications.

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MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal (PECL is an acronym for Positive ECL, PECL levels are ECL levels referenced to +5V rather than ground). If a single-ended input is to be used the VBB pin should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB supply is designed to act as the switching reference for the input of the E211 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current.

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The MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal (PECL is an acronym for Positive ECL, PECL levels are ECL levels referenced to +5V rather than ground). If a single-ended input is to be used the VBB pin should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB supply is designed to act as the switching reference for the input of the E211 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current.

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The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part–to–part skew down to an output–to–output skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111’s to accomplish the same task. The MC100LVE210 works from a –3.3V supply while the MC100E210 provides identical function and performance from a standard –4.5V 100E voltage supply.

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The MC10EL/100EL04 is a 2-input AND/NAND gate with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104 the EL04 is ideally suited for those applications which require the ultimate in AC performance.

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The MC10EL/100EL01 is a 4-input OR/NOR gate. The device is functionally equivalent to the E101 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E101 the EL01 is ideally suited for those applications which require the ultimate in AC performance.

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The EL57 is a fully differential 4:1 multiplexer which can also be used as a differential 2:1 multiplexer with the SEL0 input selecting between D0 and D1. The EL57’s fully differential architecture makes it ideal for use in low skew applications such as clock distribution. SEL1 is the most significant select line. The binary number applied to the select inputs will select the same numbered data input (i.e., 00 selects D0). Multiple VBB outputs are provided for single-ended or AC coupled interfaces. In these scenarios, the VBB output should be connected to the data bar inputs and bypassed via a 0.01µF capacitor to ground. Note that the VBB output can source/sink up to 0.5mA of current without upsetting the voltage level.

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The MC10E457/100E457 is a 3-bit differential 2:1 multiplexer. The fully differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided to ease AC coupling input signals. The higher frequency outputs provide the device with a >1.0GHz bandwidth to meet the needs of the most demanding system clock. Both, separate selects and a common select, are provided to make the device well suited for both data path and random logic applications. The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device. Note that the input clamp will take affect only if both inputs fall 2.5V below VCC.

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The MC10E/100E452 is a 5-bit differential register with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go LOW. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the D and the CLK sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5V below VCC. The fully differential design of the device makes it ideal for very high frequency applications where a registered data path is necessary.

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The MC10E/100E452 is a 5-bit differential register with differential data and clock. It features edge-triggered flip-flops and is suitable for high-frequency applications.

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The MC10/100E445 is an integrated 4-bit serial to parallel data converter. The device is designed to operate for NRZ data rates of up to 2.0Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit conversion function. The conversion sequence was chosen to convert the first serial bit to Q0, the second to Q1 etc.

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The MC10E/100E431 is a 3-bit flip-flop with differential clock, data input and data output. The asynchronous Set and Reset controls are edge-triggered rather than level controlled. This allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock edge, without the necessity of de-asserting the set/reset signal (as would be the case with a level controlled set/reset). The E431 is also designed with larger internal swings, an approach intended to minimize the time spent crossing the threshold region and thus reduce the metastability susceptibility window. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the D and the CLK sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5V below VCC.

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The MC10E/100E431 is a 3-bit edge-triggered flip-flop. The device has 3 data input pins, 3 data output pins, 1 clock input pin, 1 data set input pin, and 1 data reset input pin. The clock and data inputs are differential. This allows the device to have a larger swing and faster switching speed. The device also has input clamp functions to prevent the device from generating bias voltages when it is not in use. When the data or clock inputs are short-circuited, the device will output a determined state.

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MC10E416/100E416 is a 5-bit differential line receiving device with a 2.0GHz bandwidth high frequency output, making it ideal for buffering of very high speed oscillators.

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The MC10E416/100E416 is a 5-bit differential line receiving device. The 2.0GHz of bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. A VBB pin is available to AC couple an input signal to the device. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device.

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The MC100EL1648 is a low power voltage controlled oscillator that can be used in many applications requiring a fixed frequency clock. It is based on the VCO circuit topology of the MC1648 and is realized using Motorola's MOSAIC III advanced bipolar process technology, allowing it to operate at a higher frequency while consuming less current compared to the MC1648. The MC100EL1648 features ECL output circuitry with an on-chip termination resistor, enabling direct AC-coupling of the output signal into a transmission line.

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The MC10EL/100EL15 is a low skew 1:4 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.

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