CYPRESS Manuals

CY62256V is a 256K (32K x 8) Static RAM from Cypress Semiconductor Corporation, featuring low working voltage, low power consumption and easy expansion.

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Delta39K™ ISR™ CPLD Family features high density, high speed, low power, simple timing model, flexible clocking, multiple I/O standards, compatibility etc.

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The CY7C109B / CY7C1009B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits, with features such as high speed, low power consumption, low CMOS standby power, 2.0V data retention, automatic power-down and TTL-compatible inputs and outputs.

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This document introduces the CY62128 128K x 8 static RAM's features, including operating voltage, power consumption, and automatic power-down function.

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3.3V 32K/64K x 16/18 Dual-Port Static RAM CY7C027V/028V CY7C037V/038V is a low power, high performance, expandable dual-port static random access memory from Cypress Semiconductor Corporation that allows simultaneous access of the same memory location.

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This document describes the features and characteristics of Cypress Semiconductor Corporation's CPLD family Delta39K ISR. The series offers high density, embedded memory, high-speed operation, and support for multiple input/output standards.

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This file provides a selector guide for the Cypress PSoC development tools, including the PSoC Designer, PSoC Express, and PSoC Programmer.

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This application note describes methods for driving multiple high power LEDs with EZ-Color™. Example projects using the CY8CLED16 EZ-Color device are included to demonstrate LED dimming and color mixing using the CY3261A-RGB demonstration board.

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The CY9C62256 is a 32K x 8 magnetic nonvolatile CMOS RAM that employs an advanced magnetic RAM (MRAM) process. It provides fast read and write access, low power, and data retention for more than ten years. It is also available in JEDEC STD 28-pin DIP (600-mil), 28-pin (300-mil) SOIC, and 28-pin TSOP-1 packages.

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The CY62137CV25/30/33 and CY62137CV are high-performance CMOS static RAMs organized as 128K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular tele- phones.

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This document describes the features and characteristics of the EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge products from Cypress Semiconductor Corporation, including fixed-function mass storage device, compliance with USB 2.0 and USB Mass Storage Class standards, support for ATA/ATAPI-6 specification, support for 48-bit addressing, etc.

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This document is a user manual for CY7C68310, which mainly introduces the functions, applications, pin definitions, working principles, configuration methods and other information of the product.

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This document is the reference design notes for Cypress EZ-USB FX2LP Mass Storage reference design. It introduces the device types, the reference design contents, background information and more.

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CY22050 is an integrated phase-locked loop (PLL) general-purpose flash programmable clock generator that can generate six outputs up to 200 MHz. It can generate custom frequencies from an external reference crystal or a driven source. This product is suitable for commercial and industrial applications and offers performance guarantees for an extended temperature range. The flash-programmable technology allows for easy customization, quick turnaround on design changes and product performance enhancements, and better inventory control. The parts can be reprogrammed up to 100 times, reducing inventory of custom parts and providing an easy method for upgrading existing designs. The high-performance, low-skew, low-jitter, high-accuracy outputs make it well-suited for commercial, industrial, networking, telecomm, and other general-purpose applications. It operates at 3.3V with a 2.5V output option, making it compatible with standard and low-power systems. The product is packaged in a 16-lead TSSOP, which is an industry standard and saves board space.

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The product is a 4-Mbit (128K x 32) Pipelined Sync SRAM with registered inputs and outputs for pipelined operation, 128K × 32 common I/O architecture, 3.3V core power supply, 2.5V / 3.3V I/O operation, fast clock-to-output times (250-MHz device for 2.6 ns, 225-MHz device for 2.6 ns, 200-MHz device for 2.8 ns, 166-MHz device for 3.5 ns, 133-MHz device for 4.0 ns, 100-MHz device for 4.5 ns), provides high-performance 3-1-1-1 access rate, user-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences, separate processor and controller address strobes, synchronous self-timed writes, asynchronous output enable, offered in JEDEC-standard 100-pin TQFP and 119-ball BGA packages, and “ZZ” Sleep Mode Option.

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This document describes the features and characteristics of the CY7C130/CY7C131 and CY7C140/CY7C141 products produced by Cypress Semiconductor Corporation. These products are 1K x 8 dual-port static RAMs with true dual-ported memory cells that allow simultaneous reads of the same memory location. They are fabricated using 0.65-micron CMOS technology for optimum speed and power. The products offer high-speed access and low operating power. They support fully asynchronous operation, automatic power-down, and port-to-port communication. The CY7C130/CY7C131 can be used as a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual-port device to expand the data bus width. They are suitable for applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.

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The document describes the Ultra37000™ family of CMOS CPLDs from Cypress Semiconductor Corporation, which provides a range of high-density programmable logic solutions. The product features In-System Reprogrammable™ (ISR™) capability with JTAG interface for reconfigurability, design changes do not cause pinout or timing changes. The features include high density, simple timing model, 3.3V and 5V versions, PCI compatibility, programmable bus-hold capabilities, flexible clocking, consistent package and pinout offering, etc.

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Search for CY7C132-30PC suppliers

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The Cypress EZ-USB TX2™ is a USB 2.0 transceiver, supporting 16-bit 30MHz or 8-bit 60MHz parallel interfaces.

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This document introduces the features and characteristics of PSoC® Mixed-Signal Array, including Low Power CapSense Block, Powerful Harvard Architecture Processor, Flexible On-Chip Memory, Complete Development Tools, Precision, Programmable Clocking and Programmable Pin Configurations.

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