ATMEL AT89C51CC02 handbook
Update: 29 September, 2023
The document introduces the features and characteristics of a Rev. 4126L-CAN-01/08 product. The product adopts the 80C51 core architecture and has 256 bytes of on-chip RAM and 256 bytes of on-chip XRAM. It also has 16K bytes of on-chip flash memory with 10 years of data retention and 100K erase/write cycles, as well as a boot code section with independent lock bits. In addition, the product has 2K bytes of on-chip flash for a bootloader and supports in-system programming by on-chip boot program (CAN, UART) and IAP capability. It also features 2K bytes of on-chip EEPROM with 100K erase/write cycles, 14 sources 4-level interrupts, three 16-bit timers/counters, a full duplex UART compatible with 80C51, a maximum crystal frequency of 40 MHz, double data pointer, 21-bit watchdog timer, a 10-bit resolution analog-to-digital converter (ADC) with 8 multiplexed inputs, and a full CAN controller that is fully compliant with CAN rev.# 2.0A and 2.0B.
Brand: ATMEL
File format: PDF
Size: 1850 KB
MD5 Checksum: 6CDEC47D29DC46CF07CDBC51C8935880
Publication date: 27 March, 2012
Downloads: -
PDF Link: ATMEL AT89C51CC02 handbook PDF