MOTOROLA MPC2002 MPC2003 Manual

Update: 30 September, 2023

MPC2002 and MPC2003 are Motorola's 256KB and 512KB BurstRAM secondary cache modules for PowerPC systems. The modules are configured as 32K x 72 and 64K x 72 bits in a 136-pin dual read single inline memory module (DIMM). The module uses four of Motorola's MCM67M518 or MCM67M618 BiCMOS BurstRAMs. Bursts can be initiated with either transfer start processor (TSP) or transfer start controller (TSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst address advance (BAA) pin. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control. The cache family is designed to interface with the PowerPC 60x bus and requires external tag. PD0-PD2 are reserved for density and speed identification.

Brand: MOTOROLA

File format: PDF

Size: 239 KB

MD5 Checksum: FA2E73924AF97C7DCB6CBE93461BAB6B

Publication date: 12 July, 2012

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PDF Link: MOTOROLA MPC2002 MPC2003 Manual PDF

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