ON SEMICONDUCTOR MC10EP52 MC100EP52 3.3V 5V ECL Differential Data Clock D Flip-Flop handbook
Update: 29 September, 2023
The MC10EP/100EP52 is a differential data, differential clock D flip-flop. The device is pin and functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to VEE) the outputs of the device will remain stable. The 100 Series contains temperature compensation. Features: 330 ps Typical Propagation Delay, Maximum Frequency - 4 GHz Typical, PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V, NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V, Open Input Default State, Safety Clamp on Inputs, Q Output Will Default LOW with Inputs Open or at VEE, Pb-Free Packages are Available.
Brand: ON
File format: PDF
Size: 153 KB
MD5 Checksum: 7EA09769760F689CE61EA8F13D07947E
Publication date: 08 May, 2012
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PDF Link: ON SEMICONDUCTOR MC10EP52 MC100EP52 3.3V 5V ECL Differential Data Clock D Flip-Flop handbook PDF